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68000 68030 CPLD FPGA ARM
SHOP        

 

The Memory Board

This board provides:

64K ROM

64K RAM

The ROM base address can bet set to any one of the 256 64K pages addressable by the 68000 via DIP switches.

The RAM base address can bet set to any one of the 256 64K pages addressable by the 68000 via DIP switches.

By default, when power is first applied or following a hardware reset the RAM page is disabled and ROM appears at the RAM page instead.

A memory access cycle performed on an address anywhere in the ROM page address space (as defined by the DIP switches) enables the RAM page.

Setting the RAM page to 00h means the vector table for the processor resides in RAM, however at start-up the Stack Pointer (SP) will be loaded with a 32-bit address stored in ROM address 000000h and the Program Counter (PC) will be loaded with a 32-bit address stored in ROM address 000004h.

This behaviour can be disabled if not required.

 
 
 
 
 
 
 
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Mega-Micros Home
12 Edgefield Close
Redditch B98 7WB
ENGLAND
 
+44 (0)7973 265572
info@mega-micros.co.uk