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68000 68030 CPLD FPGA ARM
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The 68000 CPU-2 Board
This board is a second generation (enhanced) main processor board. The board contains the following:
 
Space saving PLCC 68000 CPU
POR (Power On Reset) and manual reset circuitry
The CPU/System clock oscillator module
 
Board Features:
 
CPU Halt & Reset state indicators
Binary display of the upper 2 address lines (A23 & A22)
Self Test - alone this board can be configured to 'free run'. The 68000 cycles through its entire address range performing an op-code fetch at each address.
 
Additional Features:
 
Bus Error support
Full interrupt support including NMI with optional push button NMI.
 
 
 
 
 
 
 
Disclaimer
All hardware designs, software, and information shared on this website is provided "as is"
without warranty of any kind and strictly for personal non-commercial use only.
 
 
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Mega-Micros Home
12 Edgefield Close
Redditch B98 7WB
ENGLAND
 
+44 (0)7973 265572
info@mega-micros.co.uk