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68000 68030 CPLD FPGA ARM
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ROM Adapter

This ROM Adapter plugs into the ROM socket on the Memory-2 Board replacing the default 256K x 16 (27C4096) ROM with a larger 2048K x 16 (27C322) ROM.

Additional 68000 bus signals i.e. A21, A20, and A19 must be routed to HDR1 on the ROM Adapter from the system backplane headers using fly leads.

 
Signal Backplane Header ROM Adapter HDR1
68000 bus - A21 H1 pin 29 A20
68000 bus - A20 H2 pin 29 A19
68000 bus - A19 H1 pin 28 A18
 

To map all 4MB of the 27C322 ROM into the upper 4MB region of the 68000's address space, a modification to the address decoding on the Memory-2 Board is required. IC2 controls address decoding on the Memory-2 Board and IC2 is an electrically erasable programmable logic device thus a simple firmware update is all that is required. This firmware update (gal8d.jed) and instructions on programming IC2 can be found here:

 
Memory-2/Firmware
 
Note:

For correct operation of the ROM Adapter, JB1 on the Memory-2 Board MUST be set as follows:

 
JB1 pins 1-2 open, 3-4 short, and 5-6 open
 
 
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Redditch B98 7WB
ENGLAND
 
+44 (0)7973 265572
info@mega-micros.co.uk